View NAND128W3A2BN6_227421.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NAND128-A, NAND256-A NAND512-A, NAND01G-A
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES - - - Up to 1 Gbit memory array Up to 32 Mbit spare area Cost effective solutions for mass storage applications x8 or x16 bus width Multiplexed Address/ Data Pinout compatibility for all densities 1.8V device: VDD = 1.7 to 1.95V 3.0V device: VDD = 2.7 to 3.6V
Figure 1. Packages
NAND INTERFACE - - -
TSOP48 12 x 20mm
SUPPLY VOLTAGE - -
PAGE SIZE - - x8 device: (512 + 16 spare) Bytes x16 device: (256 + 8 spare) Words x8 device: (16K + 512 spare) Bytes x16 device: (8K + 256 spare) Words Random access: 12s (max) Sequential access: 50ns (min) Page program time: 200s (typ) Fast page copy without external buffering

USOP48 12 x 17 x 0.65mm
FBGA
BLOCK SIZE - -
VFBGA55 8 x 10 x 1mm TFBGA55 8 x 10 x 1.2mm VFBGA63 9 x 11 x 1mm TFBGA63 9 x 11 x 1.2mm
PAGE READ / PROGRAM - - -
DATA INTEGRITY - - - 100,000 Program/Erase cycles 10 years Data Retention Lead-Free Components are Compliant with the RoHS Directive Error Correction Code software and hardware models Bad Blocks Management and Wear Leveling algorithms File System OS Native reference software Hardware simulation models
COPY BACK PROGRAM MODE - FAST BLOCK ERASE - Block erase time: 2ms (Typ)
RoHS COMPLIANCE

STATUS REGISTER ELECTRONIC SIGNATURE CHIP ENABLE `DON'T CARE' OPTION - Simple interface with microcontroller - - - SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions -
DEVELOPMENT TOOLS

February 2005
1/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 1. Product List
Reference Part Number NAND128R3A NAND128W3A NAND128-A NAND128R4A NAND128W4A NAND256R3A NAND256W3A NAND256-A NAND256R4A NAND256W4A NAND512R3A NAND512W3A NAND512-A NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01G-A NAND01GR4A NAND01GW4A
2/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Figure 2. Table 3. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11 FBGA55 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12 FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 13 FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 14
MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Enable (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15.Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P/E/R Controller Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SR5, SR4, SR3, SR2 and SR1 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 21.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 33 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 21. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 23.Command Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 24.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 25.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 26.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 27.Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 28.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 29.Page Read A/ Read B Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 30.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 31.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 32.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 33.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 34.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 35.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 36.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 46 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 37.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 47 Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 47 Figure 38.USOP48 - lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline . . . . . . . 48 Table 23. USOP48 - lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data48 Figure 39.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 49 Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data . . . . . . 49 Figure 40.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline . . . . . . . . 50 Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 50 Figure 41.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . 51 Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 51 Figure 42.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . . 52 Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 52
5/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 43.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 45.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SUMMARY DESCRIPTION
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed. The devices are available in the following packages: TSOP48 12 x 20mm for all products USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb and 512Mb products VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array, 0.8mm pitch) for 128Mb and 256Mb products TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for 512Mb Dual Die product VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch) for the 512Mb product TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for the 1Gb Dual Die product Two options are available for the NAND Flash family: Chip Enable Don't Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office. For information on how to order these options refer to Table 28., Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to '1'. See Table 2., Product Description, for all the devices available in the family.
7/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 2. Product Description
Timings Reference Part Number Density Bus Width Page Size Block Size Memory Array Operating Voltage 1.7 to 1.95V 32 Pages x 1024 Blocks 2.7 to 3.6V 1.7 to 1.95V 2.7 to 3.6V 1.7 to 1.95V 32 Pages x 2048 Blocks 2.7 to 3.6V 1.7to 1.95V 2.7 to 3.6V 1.7to 1.95V 32 Pages x 4096 Blocks 2.7 to 3.6V 1.7 to 1.95V 2.7 to 3.6V 1.7to 1.95V 32 Pages x 4096 Blocks 2.7 to 3.6V 1.7 to 1.95V 2.7 to 3.6V 1.7 to 1.95V 32 Pages x 8192 Blocks 2.7 to 3.6V 1.7 to 1.95V 2.7 to 3.6V Random Access Max 12s 12s 12s 12s 12s 12s 12s 12s 12s 12s 12s 12s 15s 12s 15s 12s 15s 12s 15s 12s Sequential Access Min 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns Page Program Typical 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 200s 2ms TSOP48 TFBGA63 2ms TSOP48 USOP48 VFBGA63 2ms TFBGA55 2ms TSOP48 USOP48 VFBGA55 2ms TSOP48 USOP48 VFBGA55 Block Erase Typical Package
NAND128R3A NAND128-A NAND128W3A NAND128R4A NAND128W4A NAND256R3A NAND256-A NAND256W3A NAND256R4A NAND256W4A NAND512R3A NAND512-A(1) NAND512W3A NAND512R4A NAND512W4A NAND512R3A NAND512-A NAND512W3A NAND512R4A NAND512W4A NAND01GR3A NAND01G-A NAND01GW3A NAND01GR4A NAND01GW4A 1Gbit 512Mbit 512Mbit 256Mbit 128Mbit
x8
512+16 16K+512 Bytes Bytes 256+8 Words 8K+256 Words
x16
x8
512+16 16K+512 Bytes Bytes 256+8 Words 8K+256 Words
x16
x8
512+16 16K+512 Bytes Bytes 256+8 Words 8K+256 Words
x16
x8
512+16 16K+512 Bytes Bytes 256+8 Words 8K+256 Words
x16
x8
512+16 16K+512 Bytes Bytes 256+8 Words 8K+256 Words
x16
Note: 1. Dual Die device.
Figure 2. Logic Diagram
Table 3. Signal Names
I/O8-15 Data Input/Outputs for x16 devices Data Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) Write Enable Write Protect Supply Voltage Ground Not Connected Internally Do Not Use
VDD
I/O0-7 AL CL
I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R W AL CL WP NAND Flash RB
E R RB W WP VDD VSS NC DU
VSS
AI07557C
8/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 3. Logic Block Diagram
Address Register/Counter X Decoder
AL CL W E WP R Command Interface Logic P/E/R Controller, High Voltage Generator
NAND Flash Memory Array
Page Buffer Command Register Y Decoder
I/O Buffers & Latches
RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16
AI07561c
9/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 4. TSOP48 and USOP48 Connections, x8 devices Figure 5. TSOP48 and USOP48 Connections, x16 devices
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
12 13
NAND Flash (x8)
37 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
12 13
NAND Flash (x16)
37 36
24
25
24
25
VSS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 NC NC VDD NC NC NC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 VSS
AI07585B
AI07559B
10/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 6. FBGA55 Connections, x8 devices (Top view through package)
1 2 3 4 5 6 7 8
A
DU
DU
B
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
NC
H
NC
I/O0
NC
NC
NC
VDD
J
NC
I/O1
NC
VDD
I/O5
I/O7
K
VSS
I/O2
I/O3
I/O4
I/O6
VSS
L
DU
DU
M
DU
DU
AI09366b
11/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 7. FBGA55 Connections, x16 devices (Top view through package)
1 2 3 4 5 6 7 8
A
DU
DU
B
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
I/O5
I/O7
NC
H
I/O8
I/O1
I/O10
I/O12
I/O14
VDD
J
I/O0
I/O9
I/O3
VDD
I/O6
I/O15
K
VSS
I/O2
I/O11
I/O4
I/O13
VSS
L
DU
DU
M
DU
DU
AI09365b
12/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 8. FBGA63 Connections, x8 devices (Top view through package)
1 2 3 4 5 6 7 8 9 10
A
DU
DU
DU
DU
B
DU
DU
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
NC
H
NC
I/O0
NC
NC
NC
VDD
J
NC
I/O1
NC
VDD
I/O5
I/O7
K
VSS
I/O2
I/O3
I/O4
I/O6
VSS
L
DU
DU
DU
DU
M
DU
DU
DU
DU
AI07586B
13/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 9. FBGA63 Connections, x16 devices (Top view through package)
1 2 3 4 5 6 7 8 9 10
A
DU
DU
DU
DU
B
DU
DU
DU
C
WP
AL
VSS
E
W
RB
D
NC
R
CL
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
I/O5
I/O7
NC
H
I/O8
I/O1
I/O10
I/O12
I/O14
VDD
J
I/O0
I/O9
I/O3
VDD
I/O6
I/O15
K
VSS
I/O2
I/O11
I/O4
I/O13
VSS
L
DU
DU
DU
DU
M
DU
DU
DU
DU
AI07560B
14/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
MEMORY ARRAY ORGANIZATION
The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification. In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area. Refer to Figure 10., Memory Array Organization. Bad Blocks The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. Figure 10. Memory Array Organization
x8 DEVICES
Block = 32 Pages Page = 528 Bytes (512+16)
The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details). Table 4. shows the minimum number of valid blocks in each device. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to SOFTWARE ALGORITHMS section). Table 4. Valid Blocks
Density of Device 1Gbit 512Mbits 256Mbits 128Mbits Min 8032 4016 2008 1004 Max 8192 4096 2048 1024
x16 DEVICES
Block = 32 Pages Page = 264 Words (256+8)
a Sp
re
Are
a
1st half Page 2nd half Page (256 bytes) (256 bytes) Block Page Block Page 8 bits 512 Bytes 16 Bytes
Main Area
a Sp
re
Are
a
16 bits 256 Words 8 Words
Page Buffer, 512 Bytes 512 Bytes
16 Bytes
Page Buffer, 264 Words 8 bits 256 Words 8 Words 16 bits
AI07587
15/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 3., Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/ O7 are left floating when the device is deselected or the outputs are disabled. Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled. Address Latch Enable (AL). The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable. Command Latch Enable (CL). The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. While the device is busy programming or erasing, Chip Enable transitions to High, VIH, are ignored and the device does not revert to the Standby mode. While the device is busy reading: the Chip Enable input should be held Low during the whole busy time (tBLBH1) for devices that do not present the Chip Enable Don't Care option. Otherwise, the read operation in progress is interrupted and the device reverts to the Standby mode. for devices that feature the Chip Enable Don't Care option, Chip Enable going High during the busy time (tBLBH1) will not interrupt the read operation and the device will not revert to the Standby mode. Read Enable (R). The Read Enable, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one. Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 1s (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time. Write Protect (WP). The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down. Ready/Busy (RB). The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up resistor. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below 2.5V (for 3V devices) or 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1F capacitor. The PCB track widths should be sufficient to carry the required program and erase currents VSS Ground. Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
16/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
BUS OPERATIONS
There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5., Bus Operations, for a summary. Command Input Command Input bus operations are used to give commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 23. and Table 20. for details of the timings requirements. Address Input Address Input bus operations are used to input the memory address. Three bus cycles are required to input the addresses for the 128Mb and 256Mb devices and four bus cycles are required to input the addresses for the 512Mb and 1Gb devices (refer to Tables 6 and 7, Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 24. and Table 20. for details of the timings requirements. Data Input Data Input bus operations are used to input the data to be programmed. Table 5. Bus Operations
Bus Operation Command Input Address Input Data Input Data Output Write Protect Standby E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(2) X X X VIL X I/O0 - I/O7 Command Address Data Input Data Output X X I/O8 - I/O15(1) X X Data Input Data Output X X
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 25. and Table 20. and Table 21. for details of the timings requirements. Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signature and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 26. and Table 21. for details of the timings requirements. Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. Standby When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
Note: 1. Only for x16 devices. 2. WP must be VIH when issuing a program or erase command.
17/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 6. Address Insertion, x8 Devices
Bus Cycle 1st 2nd 3rd 4th(4) I/O7 A7 A16 A24 VIL I/O6 A6 A15 A23 VIL I/O5 A5 A14 A22 VIL I/O4 A4 A13 A21 VIL I/O3 A3 A12 A20 VIL I/O2 A2 A11 A19 VIL I/O1 A1 A10 A18 A26 I/O0 A0 A9 A17 A25
Note: 1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section. 2. Any additional address input cycles will be ignored. 3. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 7. Address Insertion, x16 Devices
Bus Cycle 1st 2nd 3rd 4th(4)
Note: 1. 2. 3. 4.
I/O8I/O15 X X X X
I/O7 A7 A16 A24 VIL
I/O6 A6 A15 A23 VIL
I/O5 A5 A14 A22 VIL
I/O4 A4 A13 A21 VIL
I/O3 A3 A12 A20 VIL
I/O2 A2 A11 A19 VIL
I/O1 A1 A10 A18 A26
I/O0 A0 A9 A17 A25
A8 is Don't Care in x16 devices. Any additional address input cycles will be ignored. The 01h Command is not used in x16 devices. The 4th cycle is only required for 512Mb and 1Gb devices.
Table 8. Address Definitions
Address A0 - A7 A9 - A26 A9 - A13 A14 - A26 A8 Definition Column Address Page Address Address in Block Block Address A8 is set Low or High by the 00h or 01h Command, and is Don't Care in x16 devices
18/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
COMMAND SET
All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the ComTable 9. Commands
Bus Write Operations(1) Command 1st CYCLE Read A Read B Read C Read Electronic Signature Read Status Register Page Program Copy Back Program Block Erase Reset 00h 01h(2) 50h 90h 70h 80h 00h 60h FFh 2nd CYCLE 10h 8Ah D0h 3rd CYCLE 10h Yes Yes Command accepted during busy
mand Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 9., Commands.
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Any undefined command sequence will be ignored by the device.
19/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
DEVICE OPERATIONS
Pointer Operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see Figure 11.) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area) that is Words 0 to 255. In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the main area) that is Bytes 0 to 255, and the Read B command (01h) sets the pointer to Area B (the Figure 11. Pointer Operations
x8 Devices Area A (00h) Bytes 0- 255 Area B (01h) Area C (50h) x16 Devices Area A (00h) Words 0- 255 Area C (50h) Words 256 -263
second half of the main area) that is Bytes 256 to 511. In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the spare memory area) that is Bytes 512 to 527 or Words 256 to 263. Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see Figure 12.).
Bytes 256-511 Bytes 512 -527
A
B
C
Page Buffer
A
C
Page Buffer
Pointer (00h,01h,50h)
Pointer (00h,50h)
AI07592
20/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 12. Pointer Operations for Programming
AREA A I/O 00h 80h Address Inputs Data Input 10h 00h 80h Address Inputs Data Input 10h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. AREA B I/O 01h 80h Address Inputs Data Input 10h 01h 80h Address Inputs Data Input 10h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program. AREA C I/O 50h 80h Address Inputs Data Input 10h 50h 80h Address Inputs Data Input 10h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
ai07591
21/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles (for 512Mb and 1Gb devices) or three bus cycles (for 128Mb and 256Mb devices) are required to input the address (refer to Table 6.) of the data to be read. The device defaults to Read A mode after powerup or a Reset operation. When reading the spare area addresses: A0 to A3 (x8 devices) A0 to A2 (x16 devices) are used to set the start address of the spare area while addresses: A4 to A7 (x8 devices) A3 to A7 (x16 devices) are ignored. Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read operations as the pointer remains in the respective area. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B command is required to start another read operation in Area B. Once a read command is issued three types of operations are available: Random Read, Page Read and Sequential Row Read. Random Read. Each time the command is issued the first read is Random Read. Page Read. After the Random Read access the page data is transferred to the Page Buffer in a time of tWHBH (refer to Table 21. for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. Sequential Row Read. After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row Read operation can only be used to read within a block. If the block changes a new read command must be issued. Refer to Figure 15. and Figure 16. for details of Sequential Row Read operations. To terminate a Sequential Row Read operation set the Chip Enable signal to High for more than tEHEL. Sequential Row Read is not available when the Chip Enable Don't Care option is enabled.
22/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 13. Read (A,B,C) Operations
CL
E
W
AL
R tBLBH1 (read) RB
I/O
00h/ 01h/ 50h Command Code
Address Input
Data Output (sequentially)
Busy
ai07595
Figure 14. Read Block Diagrams
Read A Command, X8 Devices
Area B Area A Area C (1st half Page) (2nd half Page) (Spare) A9-A26(1) A0-A7 A9-A26(1) A0-A7
Read A Command, X16 Devices
Area A (main area) Area C (Spare)
Read B Command, X8 Devices
Area B Area A Area C (1st half Page) (2nd half Page) (Spare) A9-A26(1) A0-A7 A9-A26(1) A0-A3 (x8) A0-A2 (x16)
Read C Command, X8/x16 Devices
Area A Area A/ B Area C (Spare)
A4-A7 (x8), A3-A7 (x16) are don't care
AI07596
Note: 1. Highest address depends on device density.
23/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 15. Sequential Row Read Operations
tBLBH1
(Read Busy time)
tBLBH1
tBLBH1
RB Busy I/O 00h/ 01h/ 50h Command Code
ai07597
Busy 1st Page Output 2nd Page Output
Busy Nth Page Output
Address Inputs
Figure 16. Sequential Row Read Block Diagrams
Read A Command, x8 Devices
Area B Area A Area C (1st half Page) (2nd half Page) (Spare) 1st page 2nd page Nth page
Read A Command, x16 Devices
Area A (main area) Area C (Spare) 1st page 2nd page Nth page
Block
Block
Read B Command, x8 Devices
Area B Area A Area C (1st half Page) (2nd half Page) (Spare) Block 1st page 2nd page Nth page
Read C Command, x8/x16 Devices
Area A Area A/ B Area C (Spare) 1st page 2nd page Nth page
Block
AI07598
24/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is three. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. Before starting a Page Program operation a Pointer operation can be performed to point to the area to be programmed. Refer to the Pointer Operations section and Figure 12. for details. Each Page Program operation consists of five steps (see Figure 17.): 1. one bus cycle is required to setup the Page Program command 2. four bus cycles are then required to input the program address (refer to Table 6.) Figure 17. Page Program Operation
tBLBH2
3. the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer 4. one bus cycle is required to issue the confirm command to start the P/E/R Controller. 5. The P/E/R Controller then programs the data into the array. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/ E/R Controller bit SR6 is set to `1' and the Ready/ Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface.
(Program Busy time)
RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0
Read Status Register
ai07566
Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer Operations section for details.
25/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external ECC cannot be used with the Copy Back operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of Copy Back operations on the same data and or to improve the performance of the ECC. The Copy Back Program operation requires three steps: 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page into the Page Buffer. 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. Refer to Table 10. for the addresses that must be the same for the Source and Target pages. 3. Then the confirm command is issued to start the P/E/R Controller. After a Copy Back Program operation, a partialpage program is not allowed in the target page until the block has been erased. See Figure 18. for an example of the Copy Back operation. Table 10. Copy Back Program Addresses
Density 128 Mbit 256 Mbit 512 Mbit 512 Mbit DD(1) 1 Gbit DD(1)
Note: 1. DD = Dual Die.
Same Address for Source and Target Pages A23 A24 A25 A24, A25 A25, A26
Figure 18. Copy Back Operation
tBLBH1
(Read Busy time)
tBLBH2
(Program Busy time)
RB Busy I/O 00h Read Code Source Address Inputs 8Ah Copy Back Code Target Address Inputs 10h 70h SR0
Read Status Register
ai07590b
26/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to `1'. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 19.): 1. One bus cycle is required to setup the Block Erase command. 2. Only three bus cycles for 512Mb and 1Gb devices, or two for 128Mb and 256Mb devices Figure 19. Block Erase Operation
tBLBH3
(Erase Busy time)
are required to input the block address. The first cycle (A0 to A7) is not required as only addresses A14 to A26 (highest address depends on device density) are valid, A9 to A13 are ignored. In the last address cycle I/O2 to I/O7 must be set to VIL. 3. One bus cycle is required to issue the confirm command to start the P/E/R Controller. Once the erase operation has completed the Status Register can be checked for errors.
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0
Read Status Register
ai07593
Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued, refer to Table 21. for the values.
27/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new read command must be issued to continue with a Page Read or Sequential Row Read operation. The Status Register bits are summarized in Table 11., Status Register Bits. Refer to Table 11. in conjunction with the following text descriptions. Write Protection Bit (SR7). The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to `1' the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to `0' the device is protected and program or erase operations are not allowed. P/E/R Controller Bit (SR6). The Program/Erase/ Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to `0', the P/E/R Controller is active (device is busy); when the bit is set to `1', the P/E/R Controller is inactive (device is ready). Error Bit (SR0). The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to `0' the operation has completed successfully. SR5, SR4, SR3, SR2 and SR1 are Reserved.
28/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 11. Status Register Bits
Bit SR7 Name Write Protection '0' SR6 SR5, SR4, SR3, SR2, SR1 SR0 Program/ Erase/ Read Controller Reserved '1' '0' Don't Care `1' Generic Error `0' No Error - operation successful Error - operation failed Protected P/E/R C inactive, device ready P/E/R C active, device busy Logic Level '1' Not Protected Definition
Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes two steps are required: 1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h) 2. then perform two Bus Read operations - the first will read the Manufacturer Code and the second, the Device Code. Further Bus Read operations will be ignored. Refer to Table 12., Electronic Signature, for information on the addresses.
Table 12. Electronic Signature
Part Number NAND128R3A 20h NAND128W3A NAND128R4A 0020h NAND128W4A NAND256R3A 20h NAND256W3A NAND256R4A 0020h NAND256W4A NAND512R3A 20h NAND512W3A NAND512R4A 0020h NAND512W4A NAND01GR3A 20h NAND01GW3A NAND01GR4A 0020h NAND01GW4A 0059h 79h 0049h 0056h 39h 76h 0046h 0055h 36h 75h 0045h 0053h 35h 73h 0043h Manufacturer Code Device code 33h
29/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SOFTWARE ALGORITHMS
This section gives information on the software algorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 14. for value) and it is recommended to implement Garbage Collection, a Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application ST Microelectronics can provide: File System OS Native reference software, which supports the basic commands of file management. Contact the nearest ST Microelectronics sales office for more details. Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 1st Word in the spare area of the 1st page does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 20. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See the "Copy Back Program" section for more details. Refer to Table 13. for the recommended procedure to follow if an error occurs during an operation. Table 13. Block Failure
Operation Erase Program Read Recommended Procedure Block Replacement Block Replacement or ECC ECC
Figure 20. Bad Block Management Flowchart
START
Block Address = Block 0
Increment Block Address Update Bad Block table
Data = FFh? YES
NO
Last block? YES
NO
END
AI07588C
30/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 21. Garbage Collection
Old Area New Area (After GC)
Valid Page Invalid Page Free Page (Erased)
AI07599B
Garbage Collection When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm. In a Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 21.). Wear-leveling Algorithm For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm to monitor and spread the number of write cycles per block. In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequentlychanged data. The Second Level Wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
Error Correction Code An Error Correction Code (ECC) can be implemented in the Nand Flash memories to identify and correct errors in the data. For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics sales office for more details. Figure 22. Error Detection
New ECC generated during read
XOR previous ECC with new ECC
All results = zero? YES 22 bit data = 0
NO
>1 bit = zero? YES 11 bit data = 1
NO
1 bit data = 1
No Error
Correctable Error
ECC Error
ai08332
31/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Hardware Simulation Models Behavioral simulation models. Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. IBIS simulations models. IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS.
32/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 14. Table 14. Program, Erase Times and Program Erase Endurance Cycles
NAND Flash Parameters Min Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention 100,000 10 Typ 200 2 Max 500 3 s ms cycles years Unit
MAXIMUM RATING
Stressing the device above the ratings listed in Table 15., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 15. Absolute Maximum Ratings
Value Symbol TBIAS TSTG VIO (1) Parameter Min Temperature Under Bias Storage Temperature 1.8V devices Input or Output Voltage 3 V devices 1.8V devices Supply Voltage 3 V devices - 50 - 65 - 0.6 - 0.6 - 0.6 - 0.6 Max 125 150 2.7 4.6 2.7 4.6 C C V V V V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
VDD
Note: 1. Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.
33/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 16., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
NAND Flash Parameter Min 1.8V devices Supply Voltage (VDD) 3V devices Grade 1 Ambient Temperature (TA) Grade 6 1.8V devices Load Capacitance (CL) (1 TTL GATE and CL) 3V devices (2.7 - 3.6V) 3V devices (3.0 - 3.6V) 1.8V devices Input Pulses Voltages 3V devices 1.8V devices Input and Output Timing Ref. Voltages 3V devices Input Rise and Fall Times Output Circuit Resistors, Rref 1.5 5 8.35 V ns k 0.4 0.9 0 1.7 2.7 0 -40 30 50 100 VDD 2.4 Max 1.95 3.6 70 85 V V C C pF pF pF V V V Units
Table 17. Capacitance
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VIL = 0V Typ Max 10 10 Unit pF pF
Note: TA = 25C, f = 1 MHz. CIN and CI/O are not 100% tested.
34/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 18. DC Characteristics, 1.8V Devices
Symbol IDD1 IDD2 IDD3 Operating Current Parameter Sequential Read Program Erase Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices IDD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) VDD Supply Voltage (Erase and Program lockout) Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA Min VDD-0.4 -0.3 VDD-0.1 3 Typ 8 8 8 10 20 4 1.5 Max 15 15 15 50 100 10 10 VDD+0.3 0.4 0.1 Unit mA mA mA A A A A V V V V mA V
E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT= 0 to VDDmax IOH = -100A IOL = 100A VOL = 0.2V -
ILI ILO VIH VIL VOH VOL IOL (RB) VLKO
35/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 19. DC Characteristics, 3V Devices
Symbol IDD1 IDD2 IDD3 Operating Current Parameter Sequential Read Program Erase Stand-by Current (TTL), 128Mb, 256Mb, 512Mb devices IDD4 Stand-by Current (TTL) 512Mb and 1Gb Dual Die devices Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices IDD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (RB) VDD Supply Voltage (Erase and Program lockout) E=VIH, WP=0V/VDD 2.0 - 0.3 2.4 8 10 20 10 2.5 2 50 100 10 10 VDD+0.3 0.8 0.4 mA A A A A V V V V mA V Test Conditions tRLRL minimum E=VIL, IOUT = 0 mA Min Typ 10 10 10 Max 20 20 20 1 Unit mA mA mA mA
E=VDD-0.2, WP=0/VDD VIN= 0 to VDDmax VOUT= 0 to VDDmax IOH = - 400A IOL = 2.1mA VOL = 0.4V -
ILI ILO VIH VIL VOH VOL IOL (RB) VLKO
36/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 20. AC Characteristics for Command, Address, Data Input
Symbol tALLWL tALHWL tCLHWL tCLLWL tDVWH tELWL tWHALH tWHALL tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL Alt. Symbol tALS Address Latch High to Write Enable Low Command Latch High to Write Enable Low tCLS Command Latch Low to Write Enable Low tDS tCS tALH Write Enable High to Address Latch Low Write Enable High to Command Latch High tCLH Write Enable High to Command Latch Low tDH tCH tWH tWP tWC Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data Hold time E Hold time W High Hold time W Pulse Width Write Cycle time Min Min Min Min Min 10 10 20 40 60 10 10 15 25(1) 50 ns ns ns ns ns CL hold time Min 10 10 ns Data Valid to Write Enable High Chip Enable Low to Write Enable Low Write Enable High to Address Latch High AL Hold time Min 10 10 ns Data Setup time E Setup time Min Min 20 0 20 0 ns ns CL Setup time Min 0 0 ns Parameter Address Latch Low to Write Enable Low AL Setup time Min 0 0 ns 1.8V Devices 3V Unit Devices
Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns.
37/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 21. AC Characteristics for Operations
Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 tBLBH4 Write Enable High to Ready/Busy High tPROG tBERS Ready/Busy Low to Ready/Busy High Alt. Symbol tAR tRR Address Latch Low to Read Enable Low Parameter Read Electronic Signature Read cycle Min Min Min Max Max Max Max Max Max Max Max Min Min Max Min Max Max Max Min Min Max Min Min Max Max Max Max Min Min 1.8V Devices 10 10 20 12 15 500 3 5 5 10 500 10 0 60 + tr 100 20 45 100 15 15 30 30 60 35 12 15 100 80 60
(1)
3V Unit Devices 10 10 20 12 12 500 3 5 5 10 500 10 0 60 + tr 100 20 45 100 15 15 30 30 50 35 12 12 100 60 50
(1)
ns ns ns s s s ms s s s s ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns
Ready/Busy High to Read Enable Low Read Busy time, 128Mb, 256Mb, 512Mb Dual Die Read Busy time, 512Mb, 1Gb Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read
tWHBH1
tRST
Reset Busy time, during program Reset Busy time, during erase
tCLLRL tDZRL tEHBH tEHEL tEHQZ tELQV tRHBL tRHRL tRHQZ tRLRH tRLRL tRLQV
tCLR tIR tCRY tCEH tCHZ tCEA tRB tREH tRHZ tRP tRC tREA
Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Ready/Busy High (E intercepted read) Chip Enable High to Chip Enable Low(2) Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Read Enable High to Ready/Busy Low Read Enable High to Read Enable Low Read Enable High Hold time
Read Enable High to Output Hi-Z Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time(3) Read Busy time, 128Mb, 256Mb, 512Mb Dual Die Read Busy time, 512Mb, 1Gb
tWHBH tWHBL tWHRL tWLWL
tR tWB tWHR tWC
Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Write Enable Low to Write Enable Low Write Cycle time
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 34, 35 and 36. 2. To break the sequential read cycle, E must be held High for longer than tEHEL. 3. ES = Electronic Signature.
38/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 23. Command Latch AC Waveforms
CL tCLHWL
(CL Setup time)
tWHCLL
(CL Hold time)
tELWL
(E Setup time)
tWHEH
(E Hold time)
E tWLWH W tALLWL
(ALSetup time)
tWHALH
(AL Hold time)
AL tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai08028
Figure 24. Address Latch AC Waveforms
(CL Setup time)
tCLLWL
CL tELWL tWLWL tWLWL tWLWL
(E Setup time)
E tWLWH W tALHWL
(AL Setup time)
tWLWH
tWLWH
tWLWH
tWHWL tWHALL
(AL Hold time)
tWHWL tWHALL
tWHWL tWHALL
AL tDVWH tDVWH tWHDX
(Data Hold time)
(Data Setup time)
tDVWH tWHDX Adrress cycle 2 Adrress cycle 3
tDVWH tWHDX Adrress cycle 4 tWHDX
I/O
Adrress cycle 1
ai08029
Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
39/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 25. Data Input Latch AC Waveforms
tWHCLH
(CL Hold time)
CL tWHEH
(E Hold time)
E
(ALSetup time)
tALLWL
tWLWL
AL tWLWH W tDVWH
(Data Setup time)
tWLWH
tWLWH
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX tWHDX
I/O
Data In 0
Data In 1
Data In Last
ai08030
Figure 26. Sequential Data Output after Read AC Waveforms
tRLRL
(Read Cycle time)
E tRHRL
(R High Holdtime)
tEHQZ
R tRHQZ tRLQV
(R Accesstime)
tRHQZ tRLQV
tRLQV
I/O tBHRL RB
Data Out
Data Out
Data Out
ai08031
Note: 1. CL = Low, AL = Low, W = High.
40/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 27. Read Status Register AC Waveform
tCLLRL CL tWHCLL tCLHWL E tELWL W tWHRL R tDZRL tDVWH
(Data Setup time)
tWHEH
tWLWH tELQV tEHQZ
tWHDX
(Data Hold time)
tRLQV
tRHQZ
I/O
70h
Status Register Output
ai08032
Figure 28. Read Electronic Signature AC Waveform
CL
E
W
AL tALLRL1
R
(Read ES Access time)
tRLQV
I/O
90h
00h
Man. code
Device code
Read Electronic Signature Command
1st Cycle Address
Manufacturer and Device Codes
ai08039b
Note: Refer to Table 12. for the values of the Manufacturer and Device Codes.
41/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 29. Page Read A/ Read B Operation AC Waveform
CL tEHEL E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL
(Read Cycle time)
tEHQZ
tEHBH
tRHQZ
R tRLRH tBLBH1 RB tRHBL
I/O
00h or 01h Command Code
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N cycle 4 Busy
Data N
Data N+1
Data N+2
Data Last
Address N Input
Data Output from Address N to Last Byte or Word in Page
ai08033b
Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
42/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 30. Read C Operation, One Page AC Waveform
CL
E
W tWHBH tWHALL AL tALLRL2 tBHRL R
I/O
50h
Add. M cycle 1
Add. M Add. M cycle 2 cycle 3
Add. M cycle 4
Data M
Data Last
RB Command Code Address M Input Busy Data Output from M to Last Byte or Word in Area C
ai08035
Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are `don't care'.
43/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 31. Page Program AC Waveform
CL
E tWLWL
(Write Cycle time)
tWLWL
tWLWL
W tWHBL tBLBH2
(Program Busy time)
AL
R
I/O
80h
Add.N cycle 1
Add.N Add.N Add.N cycle 2 cycle 3 cycle 4
N
Last
10h
70h
SR0
RB Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program Read Status Register
ai08037
Note: Address cycle 4 is only required for 512Mb and 1Gb devices.
44/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 32. Block Erase AC Waveform
CL
E tWLWL
(Write Cycle time)
W tWHBL AL
(Erase Busy time)
tBLBH3
R
I/O
60h
Add. cycle 1
Add. Add. cycle 2 cycle 3
D0h
70h
SR0
RB Block Erase Setup Command Confirm Code Block Erase Read Status Register
ai08038b
Block Address Input
Note: Address cycle 3 is required for 512Mb and 1Gb devices only.
Figure 33. Reset AC Waveform
W
AL CL
R I/O FFh tBLBH4
(Reset Busy time)
RB
ai08043
45/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Ready/Busy Signal Electrical Characteristics Figures 35, 34 and 36 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation: Figure 35. Ready/Busy Load Circuit
(V - ) DDmax V OLmax R P min = ----------------------------------------------------------I OL + I L
So,
VDD RP
ibusy
1.85V R P min ( 1.8V ) = --------------------------3mA + I L 3.2V R P min ( 3V ) = --------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 34. Ready/Busy AC Waveform
ready VDD VOH VOL busy tf tr
AI07564B
DEVICE RB Open Drain Output
VSS
AI07563B
Figure 36. Resistor Value Versus Waveform Timings For Ready/Busy Signal
VDD = 1.8V, CL = 30pF 400 4 400
VDD = 3.3V, CL = 100pF 4
400
300 tr, tf (ns)
3 ibusy (mA) tr, tf (ns)
300
2.4
300
3 ibusy (mA)
ai07565B
200
1.7
2
200
200
2
120
1.2
100
30 1.7
0.85 60 1.7
90 0.57 1.7
1
0.43 1.7
100
100 3.6 3.6
0.8
1
0.6
0
0
3.6
3.6
1
2 RP (K)
3
4
1
2 RP (K)
3
4
tf
tr
ibusy
Note: T = 25C.
46/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PACKAGE MECHANICAL
Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
1
48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
Note: Drawing is not to scale.
Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 0.100 1.000 0.220 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.080 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283 - 0.0276 inches
47/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 38. USOP48 - lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline
1
48
e
D1
b
24
25
A2
L1
A
E1 E
DIE
A1
L
c ddd
WSOP-A
Note: Drawing not to scale.
Table 23. USOP48 - lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b c D1 ddd E E1 e L L1 q 17.00 15.40 0.50 0.55 0.25 16.80 15.30 - 0.45 - 0 0.52 0.16 0.10 12.00 Min 0.48 0.00 0.48 0.13 0.08 11.90 Max 0.65 0.10 0.56 0.23 0.17 12.10 0.06 17.20 15.50 - 0.65 - 5 0.669 0.606 0.020 0.022 0.010 0.661 0.602 - 0.018 - 0 0.020 0.006 0.004 0.472 Typ Min 0.019 0.000 0.019 0.005 0.003 0.469 Max 0.026 0.004 0.022 0.009 0.007 0.476 0.002 0.677 0.610 - 0.026 - 5 inches
48/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 39. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D D2 D1 SD
e
SE
E1
E2
E
FE FE1
FD1 FD A
b ddd A2 A1
BGA-Z61
Note: Drawing is not to scale
Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 10.00 5.60 8.80 0.80 2.00 1.20 2.20 0.60 0.40 0.40 - - 9.90 0.45 8.00 4.00 5.60 0.10 10.10 0.394 0.220 0.346 0.031 0.079 0.047 0.087 0.024 0.016 0.016 - - 0.390 0.40 7.90 0.25 0.70 0.50 8.10 0.018 0.315 0.157 0.220 0.004 0.398 0.016 0.311 Min Max 1.05 0.010 0.028 0.020 0.319 Typ Min Max 0.041 inches
49/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 40. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline
D D2 D1 SD
e
SE
E1
E2
E
FE FE1
FD1 FD A
b ddd A2 A1
BGA-Z61
Note: Drawing is not to scale
Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 10.00 5.60 8.80 0.80 2.00 1.20 2.20 0.60 0.40 0.40 - - 9.90 0.80 0.45 8.00 4.00 5.60 0.10 10.10 0.394 0.220 0.346 0.031 0.079 0.047 0.087 0.024 0.016 0.016 - - 0.390 0.40 7.90 0.50 8.10 0.25 0.031 0.018 0.315 0.157 0.220 0.004 0.398 0.016 0.311 0.020 0.319 millimeters Typ Min Max 1.20 0.010 Typ inches Min Max 0.047
50/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 41. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D D2 FD1 D1
FE e SE ddd
E
E2
E1
b
BALL "A1"
FE1 A e SD FD A2 A1
BGA-Z75
Note: Drawing is not to scale.
Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 11.00 5.60 8.80 0.80 2.50 0.90 2.70 1.10 0.40 0.40 - - - - - - 10.90 0.45 9.00 4.00 7.20 0.10 11.10 0.433 0.220 0.346 0.031 0.098 0.035 0.106 0.043 0.016 0.016 - - - - - - 0.429 0.40 8.90 0.25 0.70 0.50 9.10 0.018 0.354 0.157 0.283 0.004 0.437 0.016 0.350 Min Max 1.05 0.010 0.028 0.020 0.358 Typ Min Max 0.041 inches
51/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 42. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline
D D2 FD1 FD D1 SD
e
e E E2 E1
SE
FE FE1
BALL "A1"
ddd
A
e
b A1
A2
BGA-Z53
Note: Drawing is not to scale
Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 D2 ddd E E1 E2 e FD FD1 FE FE1 SD SE 11.00 5.60 8.80 0.80 2.50 0.90 2.70 1.10 0.40 0.40 - - - - - - 10.90 0.80 0.45 9.00 4.00 7.20 0.10 11.10 0.433 0.220 0.346 0.031 0.098 0.035 0.106 0.043 0.016 0.016 - - - - - - 0.429 0.40 8.90 0.50 9.10 0.25 0.031 0.018 0.354 0.157 0.283 0.004 0.437 0.016 0.350 0.020 0.358 millimeters Typ Min Max 1.20 0.010 Typ Min inches Max 0.047
52/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
PART NUMBERING
Table 28. Ordering Information Scheme
Example: Device Type NAND = NAND Flash Memory Density 128 = 128Mb 256 = 256Mb 512 = 512Mb 01G = 1Gb Operating Voltage R = VDD = 1.7 to 1.95V W = VDD = 2.7 to 3.6V Bus Width 3 = x8 4 = x16 Family Identifier A = 528 Bytes/ 264 Word Page Device Options 0 = No Options 2 = Chip Enable Don't Care Enabled Product Version A = First Version B = Second Version C = Third Version Package N = TSOP48 12 x 20mm (all devices) V = USOP48 12 x 17 x 0.65mm (128Mbit, 256Mbit and 512Mbit devices) ZA = VFBGA55 8 x 10 x 1mm, 6x8 ball array, 0.8mm pitch (128Mbit and 256Mbit devices) ZB = TFBGA55 8 x 10 x 1.2mm, 6x8 ball array, 0.8mm pitch (512Mbit Dual Die devices) ZA = VFBGA63 9 x 11 x 1mm, 6x8 ball array, 0.8mm pitch (512Mbit devices) ZB = TFBGA63 9 x 11 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices) Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option blank = Standard Packing T = Tape & Reel Packing E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing NAND512R3A 0 A ZA 1 T
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest ST Sales Office.
53/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
APPENDIX A. HARDWARE INTERFACE EXAMPLES
Nand Flash devices can be connected to a microcontroller system bus for code and data storage. For microcontrollers that have an embedded NAND controller the NAND Flash can be connected without the addition of glue logic (see Figure 43.). However a minimum of glue logic is required for general purpose microcontrollers that do not have an embedded NAND controller. The glue logic usually consists of a flip-flop to hold the Chip Enable, Address Latch Enable and Command Latch Enable signals stable during command and address latch operations, and some logic gates to simplify the firmware or make the design more robust. Figure 44. gives an example of how to connect a NAND Flash to a general purpose microcontroller. The additional OR gates allow the microcontroller's Output Enable and Write Enable signals to be used for other peripherals. The OR gate between A3 and CSn maps the flip-flop and NAND I/O in different address spaces inside the same chip select unit, which improves the setup and hold times and simplifies the firmware. The structure uses the microcontroller DMA (Direct Memory Access) engines to optimize the transfer between the NAND Flash and the system RAM. For any interface with glue logic, the extra delay caused by the gates and flip-flop must be taken into account. This delay must be added to the microcontroller's AC characteristics and register settings to get the NAND Flash setup and hold times. For mass storage applications (hard disk emulations or systems where a huge amount of storage is required) NAND Flash memories can be connected together to build storage modules (see Figure 45.).
Figure 43. Connection to Microcontroller, Without Glue Logic
AD17 AD16 Microcontroller G W CSn DQ PWAITEN VDD or VSS or General Purpose I/O VDD WP
AI08045b
AD(24:16)
AL CL R W E I/O RB NAND Flash
54/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Figure 44. Connection to Microcontroller, With Glue Logic
G W CSn A3 Microcontroller A2 A1 A0 DQ CLK D flip-flop D2 D1 D0 Q2 Q1 Q0
R W
NAND Flash CL AL E I/O
AI07589
Figure 45. Building Storage Modules
E1 E2 E3 En En+1
CL AL W G
NAND Flash Device 1
NAND Flash Device 2
NAND Flash Device 3
NAND Flash Device n
NAND Flash Device n+1
RB
I/O0-I/O7 or I/O0-I/O15
AI08331
RELATED DOCUMENTATION
STMicroelectronics has published a set of application notes to support the NAND Flash memories. They are available from the ST Website www.st.com. or from your local ST Distributor.
55/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
REVISION HISTORY
Table 29. Document Revision History
Date 06-Jun-2003 07-Aug-2003 27-Oct-2003 Version 1.0 2.0 3.0 First Issue Design Phase Engineering Phase Document promoted from Target Specification to Preliminary Data status. VCC changed to VDD and ICC to IDD. Title of Table 2.. changed to "Product Description" and Page Program Typical Timing for NANDXXXR3A devices corrected. Table 1., Product List, inserted on page 2. WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed. Figure 19., Cache Program Operation, modified and note 2 modified. Note removed for tWLWH timing in Table 20., AC Characteristics for Command, Address, Data Input. Meaning of tBLBH4 modified, partly replaced by tWHBH1 and tWHRL min for 3V devices modified in Table 21., AC Characteristics for Operations. References removed from RELATED DOCUMENTATION section and reference made to ST Website instead. Figure 6., Figure 7., Figure 29. and Figure 32. modified. Read Electronic Signature paragraph clarified and Figure 28., Read Electronic Signature AC Waveform, modified. Note 2 to Figure 30., Read C Operation, One Page AC Waveform, removed. Note 3 to Table 7., Address Insertion, x16 Devices removed. Only 00h Pointer operations are valid before a Cache Program operation. IDD4 removed from Table 18., DC Characteristics, 1.8V Devices. Note added to Figure 32., Block Erase AC Waveform. Small text changes. TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die devices added. Figure 19., Cache Program Operation modified. Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices) in Table 28., Ordering Information Scheme. Cache Program removed from document. TFBGA55 package specifications added (Figure 40., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline and Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data). Test conditions modified for VOL and VOH parameters in Table 19., DC Characteristics, 3V Devices. Third part number corrected in Table 1., Product List. 512 Mbit Dual Die information added to Table 10., Copy Back Program Addresses. Block Erase last address cycle modified. Definition of a Bad Block modified in Bad Block Management paragraph. RoHS COMPLIANCE added to SUMMARY DESCRIPTION. Figure 3., Logic Block Diagram modified. Document promoted from Preliminary Data to Full Datasheet status. Automatic Page 0 Read at Power-Up option no longer available. PC Demo board with simulation software removed from list of available development tools. Chip Enable (E) paragraph clarified. Rref parameter added to Table 16., Operating and AC Measurement Conditions. Description of the family clarified in the SUMMARY DESCRIPTION section. WSOP48 replaced with USOP48 package, VFBGA63 (8.5 x 15 x 1mm) replaced with VFBGA63 (9 x 11 x 1mm) package, TFBGA63 (8.5 x 15 x 1mm) replaced with TFBGA63 (9 x 11 x 1.2mm) package. Changes to Table 21., Table 18. and Table 2. Revision Details
03-Dec-2003
4.0
13-Apr-2004
5.0
28-May-2004
6.0
02-Jul-2004
7.0
01-Oct-2004
8.0
03-Dec-2004
9.0
13-Dec-2004
10.0
25-Feb-2005
11.0
56/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
57/57

▲Up To Search▲

Price & Availability of NAND128W3A2BN6

	To Download NAND128W3A2BN6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .